The present invention relates in general to computer aided integrated circuit design and, more particularly, to a computer implemented method for generating an integrated circuit design having both single-ended and differential circuits.
As integrated circuits become more dense and complex, designers have resorted to computer aided design tools to more efficiently design integrated circuits. The time required for a full scale design is drastically reduced by drawing from a library of pre-defined cells that have been fully characterized for a given wafer process flow.
One tool that is commonly used in a computer aided design system for generating an integrated circuit design is a synthesis tool. A synthesis tool receives a description of a circuit, typically in hardware description language (HDL) that functionally describes the circuit. Other description formats that describe a circuit could also be used such as a truth table, a netlist, state diagram, or an equation. The synthesis tool outputs a single-ended description of the circuit which corresponds to the actual circuit being formed on a semiconductor wafer. Synthesis tools commonly available are unable to handle differential descriptions (corresponding to differential circuitry such as CML, common mode logic) of a circuit. Synthesis tools have been designed specifically for single-ended circuitry since they make up the vast majority of digital semiconductors sold.
A netlist is a detailed interconnection of low level circuit elements, i.e. a schematic and block diagram of the circuit. The netlist is simulated to verify the proper operation and timing of the circuit. The computer aided design system will have timing information for each of the blocks or elements in the netlist. If any problem is noted during the simulation, the netlist may be updated as necessary to achieve the desired function.
Once the design is functionally correct and meets basic timing criteria, the netlist is provided to a router tool for generating an interconnected layout of the circuit. In general, gate arrays and standard cells use routers to interconnect circuit. The router performs metal interconnections and optimally places cells for the most efficient area utilization. The router also takes into account timing considerations for worst case delay paths. Actual parasitic capacitance and resistance are back-annotated from the physical layout generated by the router. The actual parasitic capacitances and resistances are fed back to the simulator and the circuit is resimulated. The updated simulation provides an accurate assessment of the circuit performance under various process and temperature conditions. This final simulation also allows changes to be made should any problems be detected. If no problems arise, masks for fabricating the circuit are generated.
Most, if not all circuit designs involve single-ended or differential logic. Single-ended logic uses 1 terminal or pin per data (logic) signal while differential logic uses 2 terminals or pins because the data signal has complimentary components. Conventional CMOS logic and TTL (Transistor Transistor Logic) are well known in the semiconductor industry as single-ended circuitry whereas Emitter Coupled Logic (ECL) is typically known as differential circuitry.
In general, prior art synthesis tools are not capable of synthesizing a differential circuit. Such tools have not yet been developed because of lack of demand from the industry. Moreover, synthesis tools cannot synthesize a combination of single-ended and differential descriptions. Again because of lack of need in the past for such tools. The dominant portion of synthesis tools for the semiconductor industry have involved single-ended synthesis.
The present trend in the electronic industry is toward low power and high speed operation. A combination of both differential and single-ended circuits may be required to meet low-power and high speed requirements simultaneously. Typical applications that demand such performance include cellular telephones, laptop computers and other portable electronics. High speed requirements encourage the use of technologies such as ECL or CML logic. To meet low power requirements, semiconductor manufacturers are reducing the operating potential of the circuits. Differential circuits can be operated at these low voltages due to their small signal swing. Furthermore, differential signals are less susceptible to noise because of the inherent common mode rejection. Single-ended circuitry can be used in sections of the circuit requiring high density and low power.
Synthesis tools for single-ended circuit design are well known in the art. However, the single-ended synthesis tools cannot synthesize differential circuits because the libraries do not support differential circuits and the single-ended synthesis tools are not set up to handle the additional information required for differential synthesis. For example, the synthesis tools are not set up to handle 2 pins per signal, nor are they set up to track important parameters for differential operation such as skew between complementary signal pairs.
Hence, a need exists for synthesis tools capable of differential synthesis and a combination of single-ended and differential synthesis.